Integrated circuit architectures comprising complementary types of devices, such as the opposite conductivity type regions of CMOS circuit structures, may typically contain one polarity type of device in the semiconductor bulk, while a second polarity type of device is contained in a well region having a conductivity type opposite to that of the substrate in which the well is formed, the well region defining a PN junction with the opposite conductivity type semiconductor material of the bulk. This PN junction creates several problems, including SCR latch up and significant leakage current through the large surface area defined between the well and the bulk. Because of these problems, bulk CMOS structures cannot be used in severe environments such as high operating temperatures and ionizing radiation. To eliminate these shortcomings of conventional CMOS well region structures, dielectrically isolated configurations, wherein the P and N regions are dielectrically isolated from one another (as by way of an oxide layer between the material of the well region and the bulk) have been employed. (Other methods of achieving dielectric isolation include providing silicon on an insulator base (e.g. silicon on sapphire (SOS)), or by forming one of the regions in a semiconductor layer which is separated from the bulk material by an insulator layer therebetween.
Now, although dielectric isolated structures obviate the above-mentioned drawbacks, they suffer from a significant limitation in that they do not provide ohmic coupling between the bottom surface of the support substrate and the device regions. This shortcoming constitutes a severe impediment to the production of dielectrically isolated implementations of complex circuit architectures, such as microprocessors, the design layout for which may take several man years.